The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and particularly, to a technique which can be advantageously applied to improvements of reliability of a non-volatile semiconductor memory device.
Known as an electrically rewritable non-volatile semiconductor memory device is a so-called AND-type Flash memory described in the Japanese Patent Application Laid-Open Publication No. 07-273231. This publication describes the following manufacturing method as a technique for improving the integration of transistors called as memory cells in the chips.
That is, a three-layer film comprised of a gate oxide film, a first polycrystal silicon layer, and a silicon nitride film is coated on a semiconductor substrate made of monocrystal silicon. These layered films are patterned into stripe shapes. Next, n-type impurities are implanted into such a portion of the semiconductor substrate that is not covered by the patterned layer film, thereby to form column lines of an n-type impurity semiconductor region on the surface of the semiconductor substrate. Next, a CVD (Chemical Vapor Deposition) oxide film is coated thereon, and thereafter, a silicon oxide film formed by the CVD method is etched thereby to form a side wall spacer on the side wall portions of the first polycrystal silicon layer and the silicon nitride film. Next, using the first polycrystal silicon layer and the side wall spacer as a mask, grooves are formed on the semiconductor substrate by anisotropic dry etching. In this manner, the n-type impurity semiconductor region is separated, and column lines and source lines are each formed. Next, a silicon oxide film is formed on the surface of the grooves. Thereafter, the second polycrystal silicon layer is coated (deposited) on the entire surface of the semiconductor substrate, and the second polycrystal silicon layer is etched back by isotropic dry etching until the silicon nitride film is exposed. Next, the surface of the second polycrystal silicon layer which has been etched back is oxidized, thereby to form an element separation region made of polycrystal silicon covered with a silicon oxide film. Subsequently, the silicon nitride film is removed, and a third polycrystal silicon layer is coated. Patterning is carried out so as to protect the first polycrystal silicon layer. Floating gates parallel to the column lines are thus formed. Next, an interlayer insulating film and a fourth polycrystal silicon layer are coated, and patterning is carried out, thereby to form row lines which are made of the forth polycrystal silicon layer and are vertical to the column lines. In this manner, the first and third polycrystal silicon layers are separated from each other, and floating gates are formed.
In the AND-type flash memory formed in this kind of method, the semiconductor device is constructed to have a non-volatile memory function by storing electrons in the floating gates. In particular, n-type impurity semiconductor regions formed in both sides of the first polycrystal silicon layer serve as source or drain regions. In this method, processing on the first polycrystal silicon layer and formation of the element separation region are achieved by a mask pattern of one single layer. Therefore, no matching margin is necessary between the gates and the element separation region, so the cell area is reduced to be small.
As a method for much higher integration of an AND-type flash memory, for example, the PCT International Publication No. WO98/44567 describes a technique in which a shallow-groove-type element separation region is formed on the main surface of a semiconductor substrate and a memory cell is formed in an active region surrounded by the element separation region. In the technique according to this publication, the element separation region is formed like a stripe, so that the active region is formed also like a stripe. The lower electrode of a floating gate is formed also like a stripe, layered on a center portion of the active region. With this lower electrode used as a mask, an ion implantation method is applied so that source lines and data lines are formed by self-alignment in the active region. Thereafter, an insulating film is filled between the lower electrodes. Upper electrodes of floating gates are formed as an upper layer thereof. In this manner, the area of the upper electrode is enlarged so that coupling with a control gate (word line) is enhanced and down-sizing is realized simultaneously.
However, the present inventors have found the following problems in the technique for forming a stripe-like element separation region as described above.
That is, many leakages have been found to occur between the sources and drains of memory elements (i.e., between source lines and data lines) in case where stripe-like element separation regions are formed and an active region is formed to be inserted between element separation regions. Therefore, this is a large obstacle which hinders securing of the reliability and the yield of the semiconductor integrated circuit device.
According to the experiments and discussions made by the present inventors, it has been found that a defective leakage is one of factors that cause an element junction leakage. FIG. 54(a) is a TEM photograph when an active region (channel portion) of a portion which causes a defect is observed. FIG. 54(b) is a schematic view in which FIG. 54(a) is traced. An active region ACL is formed between element separation regions SGI, and a floating gate electrode FG is formed on the active region ACL with a tunnel oxide film FNO inserted therebetween. On the floating gate electrode FG, a control gate electrode CG is formed with an inter-layer insulating film INS inserted therebetween. The control gate electrode CG is constructed in a two-layer structure comprised of a polycrystal silicon film and a tungsten silicide film. As shown in FIG. 54(b), a crystal defect D is formed on the active region ACL. It is considered that a leakage current is caused due to this kind of crystal defect.
Even if existence of a crystal defect does not directly involve an element defect, it is considered that it may become a factor which deteriorates the reliability. FIG. 55(a) is a circuit diagram which explains a read sequence, and FIG. 55(b) is a graph showing discharge-time-dependence of the number of defective sectors that cause a read error. As shown in FIG. 55(a), a read sequence from memory cells turns on a STD and turns off a STS, thereby to charge (precharge) electric charges from a global data line to a local data line. Next, the STS is turned on and the local source line is connected to a common source line, thereby to discharge the remaining electric charges from the local source line. Thereafter, the SDT is turned off to start sensing. In the sensing, a necessary voltage is applied to word lines (control gates), and each memory cell transistor is turned on or off in correspondence with the charge amount stored in its floating gate. If it is turned on, the electric potential of the local data line is lowered. This potential can be detected by a sense amplifier, so information in the memory cell can be extracted. At this time, if the electric potential of the local source line is not at a sufficiently low value, the following situation appears. Remaining electric charges exist in the local source line and therefore, the electric potential is not lowered, although the memory cell transistor is turned on and the potential of the local data line is lowered. That is, a read error is caused. Therefore, it is necessary to spend a sufficient time discharging electric charges from the local source line prior to the sensing. However, as shown in FIG. 55(b), there has been an experimental result showing that the number of defective sectors increases if the discharge time is elongated. Occurrence of defective sectors in accordance with increase of the discharge time is considered as being caused due to leakage currents between the source and drains (source lines and data lines) or due to leakage currents between the substrates during the discharging. The present inventors have confirmed that it is also related to a crystal defect as describe previously. Consequently, in the present situation, a discharge time of 1.6 xcexcs is required, and 500 defective sectors or so occur as can be seen from the graph. This situation is not satisfactory from the viewpoint of reliability. Particularly in case of a multi-value memory, there are demands for a high sensing accuracy and a much elongated discharge time.
As another factor which causes deterioration of the reliability, there is a problem which occurs in write-disabled cells during the writing operation. FIG. 56(a) is a graph which normally plots the shifts of a threshold voltage caused by drain disturbance. FIG. 56(b) is a circuit diagram which explains the drain disturbance. FIG. 56(c) is a cross-sectional conceptual view showing memory cell portions. For example, during the operation of writing into a memory cell M11, 18 V is applied to a control gate WL1 and 4.5 V is applied to control gates WL2 to WLn. To perform writing into the cell M11, the data line DL1 is set to 0 V so that a sufficient voltage is applied between the drain (data line) and the control gate of the cell M11, while 6 V is applied to a data line DL2 to inhibit writing into the memory cell M21. At this time, the source line S is open. Taken into consideration the memory cells M22 to M2n, their drains (data line) are applied with 6 V although their sources are open. Therefore, if a leakage current occurs between junctions of the memory cells, hot electrons are generated. A part of the hot electrons passes through the tunnel oxide film and reaches the floating gates. This part of hot electrons is very small so that problems are not particularly caused in a short time period. However, this will cause a problem in consideration of the severest conditions. Suppose, for example, a case that data is always written into memory cells M11 to M1nxe2x88x921 but is not written into the memory cell M1n at all. Even in this case, the information held in the memory cell M2n must be maintained till the end of the lifetime of the product. Where rewriting up to 105 times is guaranteed by the product and the voltage application time is 1 ms, the memory cell M2n encounters the situation as described above for a total time of 105xc3x971 msxc3x97127=12700 s since 128 memory cells on one local data line are connected (n=128). That is, in case of the severest condition, it is demanded that Vth should not be shifted even if the memory cell is exposed to the situation described above. However, as shown in FIG. 56(a), 0.1% of the sectors reach 2.1 V or more as a demanded specification in about 1000 s. This result is not sufficient for ensuring high reliability.
An object of the present invention is to reduce crystal defects inside a non-volatile memory in which stripe-like element separation regions are formed to attain higher integration.
Another object of the present invention is to reduce junction leakages in a non-volatile memory in which stripe-like element separation regions are formed to attain higher integration.
Also, another object of the present invention is to improve the reliability and yield of a non-volatile memory in which stripe-like element separation regions are formed to attain higher integration.
The above-described and other objects of the present invention as well as the noble features of the present invention will be clearly understood from the description of the present specification and the appended drawings.
Of the inventions disclosed in the present application, representative one will be explained in brief below.
A semiconductor integrated circuit device comprises: a semiconductor substrate made of silicon monocrystal; stripe-like element separation regions formed on a main surface of the semiconductor substrate; and a plurality of MISFETs (Metal Insulator Semiconductor Field Effect Transistors) or MIS-type memory elements formed in an active region between the element separation regions, the MISFETs or MIS-type memory elements being connected in series or parallel with each other, wherein a light element having a smaller mass number than silicon is introduced into the semiconductor substrate.
In this semiconductor integrated circuit device, a light element is introduced into the semiconductor substrate. Oxygen is attracted to the vicinity of the light element, and micro defects are formed, so that occurrence of dislocation defects can be reduced. According to experiments made by the present inventors, defects caused by leakages could be reduced by using a substrate to which a light element introduced, in place of a substrate which is conventionally used. That is, a conventional device uses a silicon monocrystal substrate which contains a large amount of oxygen. In this device, oxygen is drawn by a reduction atmosphere used when epitaxial growth is carried out on the surface of the silicon substrate. Therefore, the function of restricting dislocation defects does not work sufficiently. In the present invention, a light element such as nitrogen or carbon is introduced into the substrate, in place of oxygen, and is used to form memory elements having stripe-like element separation regions. Thus, an expected characteristic is attained.
The semiconductor substrate described above is advantageous for a substrate including an epitaxial layer on a base substrate to which a light element is introduced. The epitaxial growth layer has a film thickness within a range of 1 to 5 xcexcm. The base substrate is formed by a CZ (Czochralski) method.
The light element is nitrogen or carbon. Or, boron may be used. Nitrogen is introduced at a concentration of 1xc3x971013 to 1xc3x971017 atomics/cm3 and oxygen is introduced at a concentration of 6xc3x971017 to 9xc3x971017 atomics/cm3 into the semiconductor substrate or the base substrate. Or, carbon is introduced at a concentration of 1xc3x971016 to 1xc3x971017 atomics/cm3 and oxygen is introduced at a concentration of 6xc3x971017 to 9xc3x971017 atomics/cm3, into the semiconductor substrate or the base substrate.
A silicon oxide film is embedded in a shallow groove and a surface of the silicon oxide film is flattened.
Also, the stripe-like element separation regions are formed in parallel with a direction (cleavage direction) or direction equivalent thereto in which the semiconductor substrate tends to cleave most easily according to crystallography, or a direction vertical to the cleavage direction or equivalent thereto. If the main surface of the semiconductor substrate is a (100) surface or a surface equivalent thereto, stripe-like patterns of the element separation regions are formed in parallel with a direction [011] of silicon crystal or a direction equivalent thereto, or a direction [011] or a direction equivalent thereto. By forming elements in this direction, the wafer area can be used effectively and the costs can be reduced. [011] means 1 bar or bar 1.
The semiconductor substrate is cut by scribing it in the cleavage direction or the direction equivalent thereto and in the direction vertical to the cleavage direction or the direction equivalent thereto. If the main surface of the semiconductor substrate is a (100) surface or a surface equivalent thereto, the semiconductor substrate is cut by scribing it in the direction [011] of silicon crystal or the direction equivalent thereto and in the direction [011] or the direction equivalent thereto.
The size of each of the active regions in a direction parallel to stripe-like patterns of the active regions is 100 or more times longer than a size thereof in a direction vertical to the stripe-like patterns.
The MIS-type memory elements are AND-type or NAND-type non-volatile memory elements.
The semiconductor substrate or the base substrate has a crystal defect density of 3xc3x97109 cmxe2x88x923 or more according to a bulk micro defect measurement. According to discussions made by the present inventors, it is possible to prevent dislocation defects and to obtain a non-volatile memory element with a sufficiently high reliability if a defect density of 3xc3x97109 cmxe2x88x923 is found by a BMD measurement.
A method of manufacturing a semiconductor integrated circuit device, according to the present invention, comprises: a step (a) of forming a pattern having a stripe-like opening on a main surface of a semiconductor substrate and of etching the semiconductor substrate with the pattern used as a mask, thereby to form a stripe-like groove on the main surface of the semiconductor substrate; a step (b) of depositing an insulating film for filling internally the groove; a step (c) of etching or polishing the insulating film such that the insulating film remains in the groove, thereby to form an element separation region; a step (d) of depositing a polycrystal silicon film on the main surface of the semiconductor substrate, and of patterning the polycrystal silicon film into a stripe-like shape in a direction parallel to the element separation region formed like a stripe; and a step (e) of ion-implanting impurities into an active region surrounded by the element separation region, using the polycrystal silicon film formed in the stripe-like shape as a mask, thereby to form a semiconductor region which functions as a source/drain region and a wire of a MIS-type element, wherein a monocrystal silicon substrate into which a light element having a smaller mass number than silicon is introduced is used as the semiconductor substrate.
Another method of manufacturing a semiconductor integrated circuit device, according to the present invention, comprises: a step (a) of forming a pattern having a stripe-like opening on a main surface of a semiconductor substrate and of etching the semiconductor substrate with the pattern used as a mask, thereby to form a stripe-like groove on the main surface of the semiconductor substrate; a step (b) of depositing an insulating film for filling internally the groove; a step (c) of etching or polishing the insulating film such that the insulating film remains in the groove, thereby to form an element separation region; a step (d) of depositing a polycrystal silicon film on the main surface of the semiconductor substrate, and of patterning the polycrystal silicon film into a stripe-like shape in a direction vertical to the element separation region formed like a stripe; and a step (e) of ion-implanting impurities into an active region surrounded by the element separation region, using the polycrystal silicon film formed in the stripe-like shape as a mask, thereby to form a semiconductor region which functions as a source/drain region which is shared in common between adjacent MIS-type elements, wherein a monocrystal silicon substrate into which a light element having a smaller mass number than silicon is introduced is used as the semiconductor substrate.
According to the methods for manufacturing a semiconductor integrated circuit device, as described above, it is possible to form a memory element in which reduce dislocation defects of crystal are reduced and junction leakages are restricted.
A substrate in which a silicon layer is grown within a range of 1 to 5 xcexcm by epitaxial growth on a silicon monocrystal substrate to which a light element having a smaller mass number than silicon is introduced is used as the semiconductor substrate.
The light element is nitrogen or carbon. Or, boron may be used. The concentration of the nitrogen ranges from 1xc3x971013 to 1xc3x971015 atomics/cm3 and the concentration of the carbon ranges from 1xc3x971016 to 1xc3x971017 atomics/cm3.
The pattern like a stripe is formed in a direction (cleavage direction) in which the semiconductor substrate tends to cleave most easily according to crystallography or in a direction equivalent thereto, or a direction vertical to the cleavage direction or a direction equivalent thereto. Or, if the main surface of the semiconductor substrate is a (100) surface or a surface equivalent thereto, the pattern like a stripe is formed in parallel with a direction equivalent to a direction [011] of silicon crystal or a direction equivalent to a direction [011] of silicon crystal.
The active region formed like a stripe has a longer edge which is 100 or more times longer than a shorter edge.
The methods described above further comprise a step of scribing the semiconductor substrate in a direction (cleavage direction) in which the semiconductor substrate tends to cleave most easily according to crystallography or a direction equivalent thereto and in a direction vertical or equivalent to the cleavage direction and thereby cutting the semiconductor substrate into silicon chips. Or, a step of scribing the semiconductor substrate in a direction [011] of silicon crystal or a direction equivalent thereto and in a direction [011] or a direction equivalent thereto and thereby cutting the semiconductor substrate into silicon chips is comprised if the semiconductor substrate has a (100) surface or an equivalent surface as the main surface. If scribing is made in the direction in which crystal easily cleaves, dislocation defects are reduced so that a non-volatile memory element can be formed with sufficiently high reliability.